1. Field of the Invention
This invention relates to a semiconductor integrated circuit device produced through processes using charged particles such as reactive ion etching, and more particularly to a semiconductor integrated circuit device with an insulated gate.
2. Description of the Related Art
The structure of semiconductor integrated circuit devices with insulated gates is such that conducting layers are put in an electrically floating state during the manufacture. In the case of silicon gate MOS transistors, after the patterning process of polysilicon layer from which gate electrodes are formed is completed, those gate electrodes remain in an electrically floating state until the final wiring process is finished. That is, they are electrically floating throughout the intervening processes, including the source-drain region forming process and the contact-hole forming process (in which holes are made in the insulating film on the gate electrodes and in the insulating film on the wiring layer connected to the gate electrodes). In general, contact holes are made by RIE techniques. In these techniques, however, ions (charged particles) are shed on the film or layer to be etched, so that when etching reaches the gate electrode (the electrically-floating conducting layer), the gate electrode is exposed to the charged particles to be charged with electricity. If the amount of charged electricity is Q and the gate capacity is C, the voltage V applied to the gate insulating film with respect to the charged state of the gate electrode is expressed as: EQU V=Q/C (1)
As seen from equation (1), the voltage increases with the amount of charged electricity Q. A larger voltage V applies an excessive electric field on the gate insulting film, giving rise to destruction of or damage to the insulating film, and changes in the characteristics such as fluctuations in the MOS transistor threshold voltage.
More specifically, the destruction of the gate insulating film occurs when the electric field E applied to the gate insulating film exceeds the critical value EB (generally on the order of 10 MV/cm). The amount of charged electricity Q is considered to be proportional to the area of contact hole and thus is given by: EQU Q=Q0.multidot.Sc (2)
where Q0 is the total amount of charge of ions applied to a unit area and Sc the area of contact hole.
From equation (1) EQU Q=C.multidot.V (3)
Equation (3) may be changed as follows: EQU Q=C.multidot.V EQU Q=C.multidot.E.multidot.d EQU Q={.epsilon.I.multidot.Sg/d}.multidot.E.multidot.d EQU Q=.epsilon.I.multidot.Sg.multidot.E EQU E=Q/(.epsilon.I.multidot.Sg) (4)
where E is the electric field applied to the gate insulating film and d the thickness of gate insulating film (the thickness of dielectric). Substituting equation (2) into equation (4) gives: EQU E=Q0.multidot.Sc/.epsilon.I.multidot.Sg EQU E={Q0/.epsilon.I}.multidot.{Sc/Sg} (5)
where .epsilon.I is the permittivity of gate insulating film and Sg the area of gate.
Insulated-gate semiconductor integrated circuit devices are now on the way to much higher integration, increasing the relative Sc/Sg ratio. On account of this, the electric field applied to the gate insulating film often exceeds the critical value EB. Especially for semiconductor integrated circuit devices based on the design rules of 0.5 .mu.m or less, as the gate insulating film gets thinner, the film thickness d becomes smaller, so that there is a significant decrease in the breakdown voltage.